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Why can't via hole be in pad?

Why can't via hole be in pad? If I want Via in pad, how to do? Many newcomers to PCBs often have this problem when they first encounter it, because the board space is too small, dense devices lead to a small space, can not lead to fan holes, usually choose to punch the holes in the pads, which makes it much easier to connect their own lines, but often do not know what kind of problems will lead to the board? Can this be done? In order to make this issue clearly explained, it will be explained from the following two aspects: 1) Why can't via hole be in pad? 2) Under what circumstances can via holes be punched into pads? Why can't via hole be in pad In the early stage of PCB design, BGA pads are not allowed to have via holes. The main reason is that tin leakage leads to insufficient solder paste on the pads, which leads to virtual welding and unwelding of devices during device welding. Therefore, in general, holes are drilled on devices by leading out first and then drilling

Up to 30% from Oct. 2021! ST, Xilinx, Onsemi, Molex and other 12 original manufacturers shouted up again

TSMC rare increase in the full process foundry price 10 ~ 20%, the market is expected to IC design and even downstream terminal brand industry will face foundry up costs difficult to pass on, but the foundry offer although strong quarterly up does not affect many IC design industry price increase plan.   The IC design industry revealed that this wave has the strength to "fully pass on" the industry, including MediaTek, REALTEK, Novatek, ASMedia, ASPEED, etc. have been determined in the fourth quarter, the first quarter of 2022 will start to increase prices, in addition to STMicroelectronics, Xilinx, Molex, ON Semiconductor, TI, Broadcom and Intel have also been increasing chip prices.   01 STMicroelectronics raises for the third time   On 27 September, STMicroelectronics issued another notice stating that the current shortage in the semiconductor supply chain continues to severely affect our industry, with no short-term signs of recovery.   With some key supplies in the suppl

Warning: Don't let these little bugs ruin your PCB design!

01    Common errors in schematics   (1)   The ERC reporting pin has no access signal:   •   I/O attributes defined for the pins when the package is created ; •   Inconsistent grid attributes were modified when creating components or placing them, and the pins were not connected to the wires; •   The pin direction is reversed when creating the component and must be connected at the non-pin name end; •   The most common reason for this is the failure to create a project file, which is the most common mistake made by beginners . Components run outside the drawing boundary: components are not created in the center of the component library chart paper.   (2)  The network table of the created project file can only be partially transferred to the PCB : the netlist was not selected as global when it was generated.   Never use annotate when using a multi-part component that you have created yourself.   02    Common errors in PCBs   (1)  NODE not found reported on network load   • The componen