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Showing posts with the label PCB Layout Errors

Warning: Don't let these little bugs ruin your PCB design!

01    Common errors in schematics   (1)   The ERC reporting pin has no access signal:   •   I/O attributes defined for the pins when the package is created ; •   Inconsistent grid attributes were modified when creating components or placing them, and the pins were not connected to the wires; •   The pin direction is reversed when creating the component and must be connected at the non-pin name end; •   The most common reason for this is the failure to create a project file, which is the most common mistake made by beginners . Components run outside the drawing boundary: components are not created in the center of the component library chart paper.   (2)  The network table of the created project file can only be partially transferred to the PCB : the netlist was not selected as global when it was generated.   Never use annotate when using a multi-part component that you have created yourself.   02    Common errors in PCBs   (1)  NODE not found reported on network load   • The componen