Seektronics

In the past, analysts, consultants and many other experts have tried to estimate the cost of new chips using the latest process technology. They concluded that by the 3-nanometer node, only a few companies could afford it, and by the E-level node, no one might be able to afford it.   Much has changed in the last few process nodes. More and more startups are succeeding in making advanced node chips that cost far less than those highly quoted numbers. Behind those numbers are some broad changes in chip design and manufacturing. Among them:   Many advanced node chips are either highly replicated arrays of multiple cumulative processing elements for AI/ML. These are relatively simple compared to integrating different elements on a single chip, but require characterization of their thermal issues, noise, and various use cases and applications.   Advanced packaging techniques, which have become mainstream since the creation of these early estimates, allow chipmakers to bundle together chips

  Recently, WT Microelectronics announced the latest quarterly financial results. Benefiting from favorable customer demand expectations, Wenye's revenue in the third quarter was NT $167.26 billion, an increase of 42% quarter-on-quarter, an increase of 7% year on year, gross profit margin of 3.03%, a decrease of 0.55 percentage points quarter on quarter, a decrease of 0.16 percentage points year on year, revenue rate of 1.35%, a decrease of 0.39 percentage points quarter on year, a decrease of 0.53 percentage points year on year. Net profit after tax was NT $1.28 billion, up 33% quarter-on-quarter and down 38% year-over-year. Subdivided into applications, WT Microelectronics was still dominated by mobile phones in the third quarter, accounting for 28.8% of revenue, data centers and servers surged to 23.7%, communications also accounted for 12.4%, industrial and instruments 8.6%, automotive electronics 7.1%, consumer and other 9.7%, and personal computers and perimeters 9.7%. The re

  The main process of front-end design   1.  D etermine the specifications   Chip specifications, also like a list of features, is the customer to the chip design company (called Fabless, waferless design company) proposed design requirements, including the chip needs to achieve specific functional and performance requirements.   2. Define the architecture   Fabless comes up with a specific implementation architecture and the functions of each module based on the specifications proposed by the customer.   3.  HDL coding   Use hardware description language (VHDL, Verilog HDL, industry companies generally use the latter) to describe the module function in code to achieve, that is, the actual hardware circuit function is described by HDL language to form RTL (register transfer level) code.   4.  Simulation verification   Simulation verification is to check the correctness of the coding design, and the criteria for the verification is the specification developed in the first step. See if t

  Storage and computation, or computation in storage, refers to the transformation of the traditional von Neumann architecture from a computation-centric design to a data storage-centric design, that is, the use of memory for data computation, thus avoiding the "storage wall" and "power wall" generated by data handling This avoids the "storage wall" and "power wall" generated by data handling, and greatly improves the parallelism and energy efficiency of data. This architecture is especially suitable for end devices requiring large computing power and low power consumption, such as wearable devices, mobile devices, smart homes, etc.   1.  Limitations of the von Neumann architecture    The first is performance.   In the classical von Neumann architecture, data storage and computation are separated, and data is exchanged between processor CPU memory through the data bus. However, due to the different internal structures, processes, and packaging of