Seektronics

  Bare plate welding test procedure   1. After the circuit board is obtained, it is necessary to observe whether the circuit board circuit is damaged or not, and whether the welding plate is damaged or not.   2. Use a multimeter to measure whether there is short circuit between the power supply and the ground and between different power sources;   3, welding the first part of the power supply, and the power debugging successfully;   4. Weld the CPU and peripheral resistance, crystal oscillator and reset circuit again, and test the power supply and ground again after welding to avoid short circuit and thermal breakdown during welding;   Test after welding CPU: It is necessary to confirm that the crystal oscillator can start normally and reset normally. The program can be downloaded and simulated. When debugging, ensure that the corresponding IO port can be set.   IO port can be directly set to light the LED light.   5. Welding SDRAM and debugging.   6. Weld the serial port and connect i

     In general, there are two main rules for laminated design       Each routing layer must have an adjacent reference layer (power source or formation);       T he adjacent main power layer and formation should be kept at a minimum spacing to provide a large coupling capacitance          The following is an example of a stack from two to eight layers:   A single-sided PCB board and double-sided PCB board laminated   For the two-layer board, because the number of layers is small, there is no lamination problem. EMI radiation control is mainly considered from the wiring and layout;   The EMC problem of single-layer and double-layer plates is more and more prominent. The main reason for this phenomenon is that the area of the signal loop is too large, which not only produces strong electromagnetic radiation but also makes the circuit sensitive to external interference. The simplest way to improve the EMC of a line is to reduce the loop area of a critical signal.   Critical signals: From

  IC Insights has good news and bad news from November 24. The good news is that CAPEX will grow 19% year-over-year to a record $181.7 billion in 2022, IC Insights said. The bad news is that global semiconductor CAPEX is forecast to decline 19% year-over-year in 2023, which would be the biggest decline since 2008.     Semiconductor suppliers are enjoying a strong influx of orders at the start of the year due to strong post-COVID-19 economic activity. Strong demand has pushed utilization rates above 90 percent for most fabs and 100 percent for many semiconductor foundries.   In the middle of the year, however, the picture suddenly changed. Soaring inflation has quickly slowed the global economy, forcing many semiconductor makers to scale back their aggressive expansion plans.   As a result, IC Insights revised its 2022 global semiconductor CAPEX forecast to show 19 percent growth to $181.7 billion this year. The revision was down from an initial forecast of $190.4 billion and 24 percent