The main process of front-end design
1. Determine the specifications
Chip specifications, also like a list of features, is the customer to the chip design company (called Fabless, waferless design company) proposed design requirements, including the chip needs to achieve specific functional and performance requirements.
2. Define the architecture
Fabless comes up with a specific implementation architecture and the functions of each module based on the specifications proposed by the customer.
3. HDL coding
Use hardware description language (VHDL, Verilog HDL, industry companies generally use the latter) to describe the module function in code to achieve, that is, the actual hardware circuit function is described by HDL language to form RTL (register transfer level) code.
4. Simulation verification
Simulation verification is to check the correctness of the coding design, and the criteria for the verification is the specification developed in the first step. See if the design meets all the requirements of the specification. The specification is the gold standard for the correctness of the design, and all violations, which do not meet the requirements of the specification, need to revise the design and coding. Design and simulation verification is an iterative process until the verification results show full compliance with the specification criteria.
Simulation and verification tools Mentor's Modelsim, Synopsys' VCS, and Cadence's NC-Verilog are available to verify the design of RTL-level code, and individuals generally use the first Modelsim for this part, which is called the pre-simulation, and the next simulation after the synthesis of the logic part can be called the post-simulation. This part is called pre-simulation, and the next simulation after the synthesis of the logic part can be called post-simulation.
5. Logic synthesis - Design Compiler
After the simulation verification, logic synthesis is performed. The result of logic synthesis is the translation of the HDL code implemented in the design into a gate-level netlist. synthesis requires the setting of constraints, that is, you want to synthesize the circuit in terms of area, timing and other target parameters to achieve the standard.
Logic synthesis needs to be based on a specific synthesis library, and the area and timing parameters of the basic standard cell of a gate circuit are different in different libraries. Therefore, ** the choice of synthesis library is not the same, the synthesis of the circuit in the timing, area is different. **In general, after the synthesis is completed, the simulation needs to be done again to verify (this is also called post-simulation, before the simulation is called pre-simulation).
Logic synthesis tool Synopsys Design Compiler, simulation tools to choose the above three simulation tools are available.
6. STA
Static Timing Analysis (STA), static timing analysis, which also belongs to the verification category, it is mainly in the timing of the circuit to verify, ** check whether the circuit exists to establish time (setup time) and hold time (hold time) violation (violation). **This is a digital circuit basics, a register with these two timing violations, there is no way to correctly sample data and output data, so the digital chip function based on the register will definitely have problems.
STA tools are Synopsys' Prime Time.
7. Formal verification
This is also the verification category, which verifies the synthesized netlist functionally (STA is timing wise). A common method is to check for equivalence, using the functionally verified HDL design as a reference, and comparing the synthesized netlist functions to see if they are functionally equivalent. This is done to ensure that the circuit functions described in the original HDL were not changed during the logic synthesis. The flow of the front-end design is written here for now. In terms of design, the front-end design results in a gate-level netlist circuit for the chip.
Backend design flow
1. DFT
Design ForTest, design for testability. A common method of DFT is to insert a scan chain into the design, turning non-scan cells (such as registers) into scan cells. About DFT, some books have a detailed description, compared to the picture will be better to understand a little.
DFT tool Synopsys DFT Compiler.
2. Layout planning (Floor Plan)
Layout planning is to place the chip's macro cell module, in general to determine the location of various functional circuits, such as IP modules, RAM, I/O pins and so on. Layout planning can directly affect the final area of the chip.
The tool is Synopsys' Astro.
3. CTS
Clock Tree Synthesis, simply put, is the wiring of the clock. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrical connected to each register unit, so that the clock from the same clock source to each register, the clock delay difference is minimal. This is why the clock signals need to be wired separately.
The CTS tool is Synopsys' Physical Compiler.
4. Wiring (Place & Route)
The wiring here is the general signal wiring, including the alignment between various standard units (basic logic gate circuits). For example, we usually hear the 0.13um process, or 90nm process, is actually the minimum width of metal wiring can be achieved here, from a microscopic point of view is the MOS tube channel length.
The wiring tool is Synopsys' Astro.
5. Parasitic parameters extraction
Due to the resistance of the wire itself, the mutual inductance between adjacent wires, coupling capacitance inside the chip will generate signal noise, crosstalk and reflection. These effects can produce signal integrity problems, resulting in signal voltage fluctuations and variations, if serious will lead to signal distortion errors. It is very important to extract parasitic parameters for re-analysis and verification to analyze signal integrity issues.
Tool Synopsys' Star-RCXT.
6.Physical verification of layout
The physical layout of the completed wiring is verified in function and timing, and there are many verification items, such as LVS (Layout Vs Schematic) verification, which is simply the comparison verification of the layout and the logic synthesis of the gate level circuit diagram; DRC (Design Rule Checking): design rule checking, checking whether the wire spacing, wire width, etc. meet the process requirements, ERC (Electrical Rule Checking): electrical rule checking, checking electrical rule violations such as short circuit and open circuit; etc. (Electrical Rule Checking): electrical rule checking, checking short circuit and open circuit and other electrical rule violations; and so on.
The tool is Synopsys' Hercules.
The actual back-end process also includes circuit power analysis, and DFM (Design for Manufacturability) issues that arise as manufacturing processes continue to advance, which are not addressed here. The completion of physical layout verification is also the completion of the entire chip design phase, and the following is the chip manufacturing.
The physical layout is handed over to the chip foundry (called Foundry) in GDSII file format to make the actual circuit on the wafer, and then package and test it to get the actual chip we see.
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